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IS62WV51216EALL Datasheet, PDF (7/18 Pages) Integrated Silicon Solution, Inc – TTL compatible interface levels
IS62/65WV51216EALL
IS62/65WV51216EBLL
AC CHARACTERISTICS(6) (OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
Read Cycle Time
Address Access Time
Output Hold Time
, CS2 Access Time
Access Time
to High-Z Output
to Low-Z Output
, CS2 to High-Z Output
, CS2 to Low-Z Output
, Access Time
, to High-Z Output
, to Low-Z Output
tRC
tAA
tOHA
tACS1/tACS2
tDOE
tHZOE
tLZOE
tHZCS//tHZCS2
tLZCS/tLZCS2
tBA
tHZB
tLZB
45ns
Min
Max
45
-
-
45
8
-
-
45
-
22
-
18
5
-
-
18
10
-
-
45
-
18
10
-
55ns
Min
Max
55
-
-
55
8
-
-
55
-
25
-
18
5
-
-
18
10
-
-
55
-
18
10
-
unit notes
ns
1,5
ns
1
ns
1
ns
1
ns
1
ns
2
ns
2
ns
2
ns
2
ns
1
ns
2
ns
2
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
45ns
Min
Max
55ns
Min
Max
unit notes
Write Cycle Time
tWC
45
-
55
-
ns
1,3,5
,CS2 to Write End
tSCS1/tSCS2
35
-
40
-
ns
1,3
Address Setup Time to Write End
tAW
35
-
40
-
ns
1,3
Address Hold from Write End
tHA
0
-
0
-
ns
1,3
Address Setup Time
tSA
0
-
0
-
ns
1,3
, / Valid to End of Write
tPWB
35
-
40
-
ns
1,3
Pulse Width
tPWE
35
-
40
-
ns
1,3,4
Data Setup to Write End
tSD
28
-
28
-
ns
1,3
Data Hold from Write End
tHD
0
-
0
-
ns
1,3
LOW to High-Z Output
tHZWE
-
18
-
18
ns
2,3
HIGH to Low-Z Output
tLZWE
10
-
10
-
ns
2,3
Notes:
1. Tested with the load in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are
measured when the output enters a high impedance state. Not 100% tested.
3. The internal write time is defined by the overlap of =LOW, CS2=HIGH, ( or )=LOW, and =LOW. All four conditions must be in valid
states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
4. tPWE > tHZWE + tSD when OE is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby
mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
Integrated Silicon Solution, Inc.- www.issi.com
7
Rev. B
10/21/2014