IS62WV51216EALL Datasheet, PDF (10/18 Pages) Integrated Silicon Solution, Inc – TTL compatible interface levels

IS62/65WV51216EALL
IS62/65WV51216EBLL
WRITE CYCLE NO. 1 (
ADDRESS
CONTROLLED,
= HIGH OR LOW)
tWC
tSCS1
tHA
CS2
,
DOUT
DIN
tSCS2
tAW
tPWE
tPWB
tSA
tHZWE
DATA UNDEFINED⁽¹⁾
DATA UNDEFINED⁽²⁾
tLZWE
tSD
tHD
DATA VALID
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if
Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 2 (
ADDRESS
CONTROLLED:
IS HIGH DURING WRITE CYCLE)
tWC
goes high before
tSCS1
tHA
tSCS2
CS2
tAW
tPWE
DOUT
DIN
tPWB
tSA
tHZWE
DATA UNDEFINED⁽¹⁾
DATA UNDEFINED⁽²⁾
HIGH-Z
tLZWE
tSD
tHD
DATA VALID
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if
Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
goes high before
Integrated Silicon Solution, Inc.- www.issi.com
10
Rev. B
10/21/2014