IS62WV51216EALL Datasheet, PDF (12/18 Pages) Integrated Silicon Solution, Inc – TTL compatible interface levels

IS62/65WV51216EALL
IS62/65WV51216EBLL
WRITE CYCLE NO. 4 ( & CONTROLLED)
ADDRESS
tWC
tWC
LOW
HIGH
CS2
tSA
tHA
tSA
tPWB
tHA
tPWB
tHZWE
tLZWE
DOUT
DATA UNDEFINED⁽¹⁾
tHD
tHD
tSD
tSD
DIN
DATA
VALID
DATA
VALID
Notes:
1. If is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous
READ operation will drive IO BUS.
2. Due to the restriction of note1, is recommended to be HIGH during write period.
3. Note stays LOW in this example. If toggles, tPWE and tHZWE must be considered.
Integrated Silicon Solution, Inc.- www.issi.com
12
Rev. B
10/21/2014