IS62VV25616L Datasheet, PDF (7/10 Pages) Integrated Silicon Solution, Inc – 256K x 16 LOW VOLTAGE, 1.8V ULTRA LOW POWER CMOS STATIC RAM

IS62VV25616LL
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol Parameter
-70
-85
Min. Max.
Min. Max.
Unit
tWC
Write Cycle Time
70 —
85 —
1ns
tSCE
CE to Write End
65 —
70 —
ns
tAW
Address Setup Time to Write End
65 —
70 —
ns
tHA
Address Hold from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
ns
tPWB
LB, UB Valid to End of Write
60 —
70 —
ns
tPWE
WE Pulse Width
55 —
60 —
ns
tSD
Data Setup to Write End
30 —
35 —
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE⁽³⁾ WE LOW to High-Z Output
— 30
— 30
ns
tLZWE⁽³⁾ WE HIGH to Low-Z Output
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1^(1,2) (CE Controlled, OE = HIGH or LOW)
ADDRESS
CE
WE
UB, LB
DOUT
DIN
t SA
DATA UNDEFINED
t WC
VALID ADDRESS
t SCS
t HA
t AW
t PWE1
t PWE2
t PBW
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
UB_CSWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of
the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. B
08/07/02