IS62VV25616L Datasheet, PDF (5/10 Pages) Integrated Silicon Solution, Inc – 256K x 16 LOW VOLTAGE, 1.8V ULTRA LOW POWER CMOS STATIC RAM

IS62VV25616LL
ISSI ^®
POWER SUPPLY CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
Test Conditions
-70
-85
Min. Max. Min. Max.
Unit
ICC
Vdd Dynamic Operating VDD = Max.,
Supply Current
IOUT = 0 mA, f = fMAX
Com.
Ind.
— 30
— 30
mA
— 35
— 35
ICC1
Operating Supply
VDD = Max.,
Current
IOUT = 0 mA, f = 1 MHZ
Com.
Ind.
—3
—3
mA
—3
—3
ISB1
TTL Standby Current VDD = Max.,
(TTL Inputs)
VIN = VIH or VIL
CE ≥ VIH , f = 0
OR
Com.
Ind.
— 0.3
— 0.3
mA
— 0.3
— 0.3
ULB Control
Vdd = Max., VIN = VIH or VIL
CE = VIL, f = 0, UB = VIH, LB = VIH
ISB2
CMOS Standby
VDD = 1.95V.,
Current (CMOS Inputs) CE ≥ VDD – 0.2V,
VIN ≥ VDD – 0.2V, or
VIN ≤ 0.2V, f = 0
Com.
Ind.
OR
ULB Control
VDD = 1.95V., CE = VIL
VIN ≤ 0.2V, f = 0; UB / LB = VDD – 0.2V
— 10
— 10
µA
— 10
— 10
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol
Parameter
-70
-85
Min. Max.
Min. Max.
Unit
tRC
Read Cycle Time
70
—
85
—
ns
tAA
Address Access Time
—
70
—
85
ns
tOHA
Output Hold Time
10
—
10
—
ns
tACE
CE Access Time
—
70
—
85
ns
tDOE
OE Access Time
—
35
—
40
ns
tHZOE⁽²⁾
OE to High-Z Output
—
25
—
25
ns
tLZOE⁽²⁾
OE to Low-Z Output
5
—
5
—
ns
tHZCE⁽²⁾
CE to High-Z Output
0
25
0
25
ns
tLZCE⁽²⁾
CE to Low-Z Output
10
—
10
—
ns
tBA
LB, UB Access Time
—
70
—
85
ns
tHZB
LB, UB to High-Z Output
0
25
0
25
ns
tLZB
LB, UB to Low-Z Output
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. B
08/07/02