IS62U6416LL Datasheet, PDF (7/9 Pages) Integrated Silicon Solution, Inc – 64K x 16 LOW VOLTAGE, ULTRA-LOW POWER CMOS STATIC RAM

IS62U6416LL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,2) (Over Operating Range)
Symbol
tWC
tSCE
tAW
tHA
tSA
tPWB
tPWE
tSD
tHD
tHZWE⁽³⁾
tLZWE⁽³⁾
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-200
Min. Max.
200
—
160
—
160
—
0
—
0
—
160
—
160
—
160
—
0
—
—
50
20
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V,
input pulse levels of 0.4V to 1.8V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All
signals must be in valid states to initiate a Write, but any one can go inactive to terminate the
Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the
signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
DATA RETENTION CHARACTERISTICS
Symbol
VDR
IDR
Parameter
Vcc for Data Retention
Data Retention Current
tSDR
Data Retention Set up Time
tRDR
Recovery Time
Test Condition
CE ≥ VCC – 0.2V
VCC = VDR
CE ≥ VCC – 0.2V
See Data Retention Waveform
See Data Retention Waveform
Min. Max.
1.5 —
— 5.0
0—
tRC
—
DATA RETENTION TIMING DIAGRAM
tSDR
DATA RETENTION MODE
tRDR
VCC
1.8V
VIH
VDR
CE
GND
CE ≥ VCC – 0.2V
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION SR034-0C
12/09/98
ISSI ^®
1
2
3
4
5
6
7
Unit
V
8
µA
ns
9
ns
10
11
12
7