IS62LV5128LL Datasheet, PDF (7/10 Pages) Integrated Silicon Solution, Inc – 512K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM

IS62LV5128LL
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range, Standard and Low Power)
Symbol
Parameter
-70
-85
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
70
—
85
—
ns
tSCE
CE to Write End
65
—
70
—
ns
tAW
Address Setup Time to Write End
65
—
70
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
ns
tPWE⁽⁴⁾
WE Pulse Width
60
—
60
—
ns
tSD
Data Setup to Write End
30
—
35
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE⁽²⁾
WE LOW to High-Z Output
—
33
—
35
ns
tLZWE⁽²⁾
WE HIGH to Low-Z Output
5
—
5
—
ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0.4Vto2.2VandoutputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. TheinternalwritetimeisdefinedbytheoverlapofCELOWandWE LOW. AllsignalsmustbeinvalidstatestoinitiateaWrite,butanyonecangoinactivetoterminatethe
Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW)
ADDRESS
CE
WE
DOUT
DIN
tWC
tSCE
tHA
tAW
tPWE⁽⁴⁾
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. D
05/04/01