IS62LV5128LL Datasheet, PDF (4/10 Pages) Integrated Silicon Solution, Inc – 512K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM

IS62LV5128LL
ISSI ^®
POWER SUPPLY CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
Test Conditions
-70
Min. Max.
-85
Min. Max.
ICC
Vcc Dynamic VCC = Max., CE = VIL Com.
Operating
IOUT = 0 mA, f = fMAX
Ind.
Supply Current
—
40
—
45
—
35
—
40
ICC1
Operating Supply VCC = Max.,
Current
IOUT = 0 mA, f = 0
Com.
Ind.
—
5
—
5
—
5
—
5
ISB1
TTL Standby VCC = Max.,
Current
VIN = VIH or VIL,
(TTL Inputs)
CE1 ≥ VIH, f = 0
Com.
Ind.
—
0.4
—
1.0
—
0.4
—
1.0
ISB2
CMOS Standby VCC = Max., f = 0
Com.
Current
CE1 ≥ VCC – 0.2V,
Ind.
(CMOS Inputs) or VIN ≥ VCC – 0.2V,
VIN ≤ 0.2V
—
10
—
10
—
10
—
10
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Unit
mA
mA
mA
µA
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol
Parameter
-70
-85
Min.
Max.
Min.
Max.
Unit
tRC
Read Cycle Time
70
—
85
—
ns
tAA
Address Access Time
—
70
—
85
ns
tOHA
Output Hold Time
10
—
15
—
ns
tACE
CE Access Time
—
70
—
85
ns
tDOE
OE Access Time
—
35
—
40
ns
tHZOE⁽²⁾
OE to High-Z Output
—
25
—
25
ns
tLZOE⁽²⁾
OE to Low-Z Output
5
—
5
—
ns
tLZCE⁽²⁾
CE to Low-Z Output
10
—
10
—
ns
tHZCE⁽²⁾
CE to High-Z Output
0
25
0
25
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
05/04/01