IS62LV2568LL Datasheet, PDF (7/10 Pages) Integrated Silicon Solution, Inc – 256K x 8 LOW POWER and LOW Vcc CMOS STATIC RAM

IS62LV2568LL
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range, Standard and Low Power)
Symbol
Parameter
-70
-85
Min.
Max.
Min.
Max.
Unit
tWC
Write Cycle Time
70
—
85
—
ns
tSCE1
CE1 to Write End
65
—
70
—
ns
tSCE2
CE2 to Write End
65
—
70
—
ns
tAW
Address Setup Time to Write End
65
—
70
—
ns
tHA
Address Hold from Write End
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
ns
tPWE⁽⁴⁾
WE Pulse Width
60
—
60
—
ns
tSD
Data Setup to Write End
30
—
35
—
ns
tHD
Data Hold from Write End
0
—
0
—
ns
tHZWE⁽²⁾
WE LOW to High-Z Output
—
33
—
25
ns
tLZWE⁽²⁾
WE HIGH to Low-Z Output
5
—
5
—
ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof1.3V,inputpulselevelsof0.4Vto2.2VandoutputloadingspecifiedinFigure1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. TheinternalwritetimeisdefinedbytheoverlapofCE1LOW,CE2HIGHandWELOW. AllsignalsmustbeinvalidstatestoinitiateaWrite,butanyonecangoinactiveto
terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW)
ADDRESS
CE1
CE2
WE
DOUT
tWC
tSCE1
tSCE2
tAW
tPWE⁽⁴⁾
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tSD
tHA
tLZWE
tHD
DIN
DATA-IN VALID
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. B
05/03/00