24C128 Datasheet, PDF (7/12 Pages) Integrated Silicon Solution, Inc – 131,072-bit 2-WIRE SERIAL CMOS EEPROM

IS24C128
Figure 4. Data Validity Protocol
SCL
SDA
Data Change
Data Stable
Data Stable
Figure 5. Slave Address
BIT 7 6 5 4 3 2 1 0
1 0 1 0 0 A1 A0 R/W
ISSI ^®
Figure 6. Byte Write
S
W
T
R
S
A
R
Device
I
T
T
O
T Address E Word Address
Word Address
Data
P
SDA
A
A
A
A
Bus
Activity
C**
C
C
C
K
K
K
K
M
L
M
S
B
S
B
S
B
* = Don't care bits
R/W
Figure 7. Page Write
S
W
T
R
A
R
Device
I
T
T ^Address E ^{Word Address (n) Word Address (n)}
Data (n)
SDA
A
A
A
A
Bus
Activity
C**
C
C
C
K
K
K
K
M
L
S
S
B
B
R/W
* = Don't care bits
Data (n+1)
A
C
K
S
T
O
Data (n+63) P
A
C
K
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
PRELIMINARYINFORMATION Rev.00A
03/11/03