IS62C256 Datasheet, PDF (6/8 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW POWER CMOS STATIC RAM

IS62C256
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol Parameter
-45 ns
-70ns
Min. Max.
Min. Max.
Unit
tWC Write Cycle Time
tSCS CS to Write End
45 —
70
—
ns
35 —
60
—
ns
tAW Address Setup Time to Write End
25 —
60
—
ns
tHA Address Hold from Write End
0—
0
—
ns
tSA Address Setup Time
WE tPWE⁽⁴⁾
Pulse Width
0—
0
—
ns
25 —
55
—
ns
tSD Data Setup to Write End
20 —
30
—
ns
tHD Data Hold from Write End
0—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CS LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS Controlled, OE is HIGH or LOW) ^{(1 )}
t WC
ADDRESS
CS
WE
DOUT
DIN
VALID ADDRESS
t SA
t SCS
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
CS_WR1.eps
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99