IS62C256 Datasheet, PDF (4/8 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW POWER CMOS STATIC RAM

IS62C256
ISSI ^®
DATA RETENTION CHARACTERISTICS
Symbol
VDR
IDR1
IDR2
Parameter
VCC for retention of data
Data retention current
Data retention current
Test Conditions
VDR = 3.0V, TA = 0°C to +25°C
VDR = 3.0V, TA = 0°C to +70°C
Min.
2.0
—
—
Max.
—
200
200
Units
V
µA
µA
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
tRC Read Cycle Time
tAA Address Access Time
tOHA
tACS
tDOE
tLZOE⁽²⁾
tHZOE⁽²⁾
tLZCS⁽²⁾
tHZCS⁽²⁾
tPU⁽³⁾
tPD⁽³⁾
Output Hold Time
CS Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CS to Low-Z Output
CS to High-Z Output
CS to Power-Up
CS to Power-Down
-45 ns
-70 ns
Min. Max.
Min. Max.
Unit
45 —
70
—
ns
— 45
—
70
ns
2—
2
—
ns
— 45
—
70
ns
— 25
—
35
ns
0—
0
—
ns
0 20
0
25
ns
3—
3
—
ns
0 20
0
25
ns
0—
0
—
ns
— 30
—
50
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480 Ω
5V
OUTPUT
100 pF
Including
jig and
scope
255 Ω
Figure 1.
4
480 Ω
5V
OUTPUT
5 pF
Including
jig and
scope
Figure 2.
255 Ω
Integrated Silicon Solution, Inc. — 1-800-379-4774
SR072-1E
05/12/99