IS62C1024 Datasheet, PDF (6/8 Pages) Integrated Circuit Solution Inc – 128K x 8 HIGH-SPEED CMOS STATIC RAM

IS62C1024
ISSI ^®
READ CYCLE NO. 2^(1,3)
ADDRESS
OE
CE1
CE2
DOUT
tRC
tAA
tDOE
tLZOE
tACE1/tACE2
tLZCE1/
tLZCE2
HIGH-Z
tOHA
tHZOE
tHZCE
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range, Standard and Low Power)
Symbol Parameter
-35
-45
-55
-70
Min. Max.
Min. Max.
Min. Max.
Min. Max.
Unit
tWC
Write Cycle Time
35 —
45 —
55 —
70 —
ns
tSCE1
CE1 to Write End
25 —
35 —
50 —
60 —
ns
tSCE2
CE2 to Write End
25 —
35 —
50 —
60 —
ns
tAW
Address Setup Time to Write End 25 —
35 —
45 —
60 —
ns
tHA
Address Hold from Write End
0—
0—
0—
0—
ns
tSA
Address Setup Time
0—
0—
0—
0—
ns
tPWE⁽⁴⁾
WE Pulse Width
25 —
35 —
40 —
50 —
ns
tSD
Data Setup to Write End
20 —
25 —
25 —
30 —
ns
tHD
Data Hold from Write End
0—
0—
0—
0—
ns
tHZWE⁽²⁾
WE LOW to High-Z Output
— 10
— 15
— 20
— 25
ns
tLZWE⁽²⁾
WE HIGH to Low-Z Output
3—
5—
5—
5—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
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Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00