IS61WV5128EDBLL-10TLI Datasheet, PDF (6/14 Pages) Integrated Silicon Solution, Inc – 512K x 8 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC

IS61/64WV5128EDBLL
AC WAVEFORMS
READ CYCLE NO. 1^(1,2) (Address Controlled) (CE = OE = Vil)
ADDRESS
DOUT
t RC
t AA
t OHA
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2^(1,3) (CE and OE Controlled)
ADDRESS
OE
CE
DOUT
t LZCE
HIGH-Z
t RC
t AA
t DOE
t LZOE
t ACE
t OHA
t HZOE
t HZCE
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = Vil.
3. Address is valid prior to or coincident with CE LOW transitions.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B
11/08/2011