IS61WV5128EDBLL-10TLI Datasheet, PDF (5/14 Pages) Integrated Silicon Solution, Inc – 512K x 8 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC

IS61/64WV5128EDBLL
AC TEST CONDITIONS
Parameter

Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level (VRef)
Output Load
Unit
(2.4V-3.6V)
0.4V to Vdd-0.3V
1V/ ns
Vdd/2
See Figures 1 and 2
AC TEST LOADS
OUTPUT
ZO = 50Ω
50Ω
1.5V
30 pF
Including
jig and
scope
Figure 1.
1
2
3
3.3V
319 Ω
4
OUTPUT
5 pF
Including
jig and
scope
353 Ω
5
6
Figure 2.
7
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
-8 -10 -20
8
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Unit
trc
Read Cycle Time
8—
10 —
20 —
ns
taa
Address Access Time
—8
toha
Output Hold Time
2.0 —
— 10
2.0 —
— 20
ns
2.5 —
ns
9
tace
CE Access Time
—8
— 10
— 20
ns
tdoe
OE Access Time
— 4.5
— 4.5
—8
ns
thzoe⁽²⁾ OE to High-Z Output
—3
—4
—8
ns
10
tlzoe⁽²⁾
OE to Low-Z Output
0—
0—
0—
ns
thzce⁽²
CE to High-Z Output
03
04
08
ns
tlzce⁽²⁾
tpu
CE to Low-Z Output
Power Up Time
3—
0—
3—
0—
3—
ns
0—
ns
11
tpd
Power Down Time
—8
— 10
— 20
ns
Notes:
1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage.
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Integrated Silicon Solution, Inc. — www.issi.com
5
Rev. B
11/08/2011