IS61QDB41M36 Datasheet, PDF (6/28 Pages) Integrated Silicon Solution, Inc – 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
ISSI ^®
Application Example
2M x 18
SRAM #1
SRAM #4
ZQ ^R=250Ω
ZQ ^R=250Ω
Vt
R
D_0–17
Q_0–17
SA R W BW₀ BW₁ C C K K
D_0–17
Q_0–17
SA R W BW₀ BW₁ C C K K
Data In 0–71
Data Out 0–71
Address 0–75
R
W
BW_0–7
Memory
Controller
Return CLK
Source CLK
Return CLK
Source CLK
Vt
Vt
R=50Ω Vt=V_REF
Vt
Vt
R
Power-Up and Power-Down Sequences
The power supplies must be powered up in the following order:
1. V_DD
2. V_DDQ
3. V_REF
4. Inputs
The power-down sequence must be the reverse. V_DDQ can be allowed to exceed V_DD by no more than 0.6V.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04