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| IS61QDB41M36 Datasheet, PDF (14/28 Pages) Integrated Silicon Solution, Inc – 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs | |||
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36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
ISSI ®
Capacitance (TA = 0 to +70° C, VDD = 1.8V -5%, +5%, f = 1MHz)
Parameter
Symbol
Test Condition
Input capacitance
Data-in capacitance (D0âD35)
Data-out capacitance (Q0âQ35)
Clocks Capacitance (K, K, C, C)
CIN
CDIN
COUT
CCLK
VIN = 0V
VDIN = 0V
VOUT = 0V
VCLK = 0V
Maximum
4
4
4
4
Units
pF
pF
pF
pF
DC Electrical Characteristics (TA = 0 to +70° C, VDD = 1.8V -5%, +5%)
Parameter
Symbol
Minimum Maximum Units
Notes
x36 average power supply operating current
(IOUT = 0, VIN = VIH or VIL)
IDD50
â
500
mA
1
x18 average power supply operating current
(IOUT = 0, VIN = VIH or VIL)
Power supply standby current
(R = VIH, W = VIH. All other inputs = VIH or VIH, IIH = 0)
Input leakage current, any input (except JTAG)
(VIN = VSS or VDD)
Output leakage current
(VOUT = VSS or VDDQ, Q in High-Z)
Output âhighâ level voltage (IOH = -6mA)
Output âlowâ level voltage (IOL = +6mA)
JTAG leakage current
(VIN = VSS or VDD)
1. IOUT = chip output current.
2. Minimum impedance output driver.
3. JEDEC Standard JESD8-6 Class 1 compatible.
4. For JTAG inputs only.
5. Currents are estimates only and need to be verified.
IDD50
â
500
mA
1
ISB
â
200
mA
1
ILI
-2
+2
µA
ILO
-5
+5
µA
VOH
VDDQ -.4
VDDQ
V
2, 3
VOL
VSS
VSS+.4
V
2, 3
ILIJTAG
-100
+100
µA
4
14
Integrated Silicon Solution, Inc. â 1-800-379-4774
Rev. B
07/09/04
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