IS61QDB41M36 Datasheet, PDF (17/28 Pages) Integrated Silicon Solution, Inc – 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 4) Synchronous SRAMs

36 Mb (1M x 36 & 2M x 18)
QUAD (Burst of 4) Synchronous SRAMs
ISSI ^®
AC Characteristics (T_A = 0 to +70^oC, V_DD = 1.8V -5%, +5%)
Parameter
Symbol
50
(200MHz)
Min Max
Clock
Cycle time (K, K, C, C)
t_KHKH 5.0
Clock phase jitter (K, K, C, C)
t_KC-VAR
Clock high pulse (K, K, C, C)
t_KHKL 2.0
Clock low pulse (K, K, C, C)
t_KLKH 2.0
Clock to clock (K_H>K_H, C_H>C_H)
t_KHKH 2.2
Clock to data clock (K_H>C_H, K_H>C_H) t_KHCH 0.0
DLL lock (K, C)
t_KC-lock 1024
K static to DLL reset
t_KC-reset 30
Output Times
7.5
0.2
2.75
2.3
C, C high to output valid
C, C high to output hold
C, C high to echo clock valid
C, C high to echo clock hold
CQ, CQ High to output valid
CQ, CQ high to output hold
C High to output high-Z
C High to output low-Z
Setup Times
t_CHQV
t_CHQX
t_CHCQV
t_CHCQX
t_CQHQV
t_CQHQX
t_CHQZ
t_CHQX1
-0.38
-0.36
-0.4
-0.38
0.38
0.36
0.38
0.38
Address valid to K, K rising edge
t_AVKH
0.4
—
Control inputs valid to K rising edge t_IVKH
0.4
—
Data-in valid to K, K rising edge
t_DVKH
0.4
—
Hold Times
K rising edge to address hold
t_KHAX
0.4
—
K rising edge to control inputs hold
t_KHIX
0.4
—
K, K rising edge to data-in hold
t_KHDX
0.4
—
Units Notes
ns
ns
ns
ns
ns
ns
cycle
cycle
ns 1, 3
ns 1, 3
ns
3
ns
3
ns 1, 3
ns 1, 3
ns 1, 3
ns 1, 3
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
1. See AC Test Loading on page 16.
2. During normal operation, V_IH, V_IL, T_RISE, and T_FALL of inputs must be within 20% of V_IH, V_IL, T_RISE, and T_FALL of clock.
3. If C, C are tied high, then K, K become the references for C, C timing parameters.
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
07/09/04