IS61NLF25672 Datasheet, PDF (6/35 Pages) Integrated Silicon Solution, Inc – 256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI ^®
165-PIN PBGA PACKAGE CONFIGURATION 1024K x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A NC
A
CE
BWb
NC
CE2
CKE
ADV
A
A
A
B NC
A
CE2 _NC
BWa CLK
WE
OE
A
A
NC
C NC
NC
VDDQ Vss
Vss _Vss
Vss
Vss VDDQ NC DQPa
D NC DQb VDDQ VDD
Vss Vss
Vss
VDD
VDDQ
NC
DQa
E NC DQb ^VDDQ VDD
Vss Vss
Vss
VDD _VDDQ
NC
DQa
F
NC
DQb ^VDDQ _VDD
Vss Vss
Vss
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ _VDD
H NC VDD
NC ^VDD
Vss Vss Vss
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
VDD
NC
NC
ZZ
J _DQb
NC
VDDQ _VDD
Vss
Vss
Vss
VDD _{VDDQ DQa NC}
K _{DQb NC VDDQ VDD}
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
L _{DQb NC VDDQ VDD}
Vss Vss
Vss
VDD
VDDQ
DQa ^NC
M DQb NC ^VDDQ VDD
Vss ^Vss
Vss
VDD _VDDQ
DQa
NC
N DQPb NC VDDQ Vss
NC
NC
NC
Vss _VDDQ
NC
NC
P NC ^NC
A
A
TDI
A1* TDO
A
A
A
NC
R MODE ^NC
A
A
TMS
A0*
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a,b)
OE
ZZ
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
Output Enable
Power Sleep Mode
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQx
DQPx
VDDQ
VSS
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
6
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/26/05