IS61NLF25672 Datasheet, PDF (5/35 Pages) Integrated Silicon Solution, Inc – 256K x 72, 512K x 36 and 1M x 18 18Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

IS61NLF25672/IS61NVF25672
IS61NLF51236/IS61NVF51236
IS61NLF102418/IS61NVF102418
ISSI ^®
PIN CONFIGURATION — 512K X 36, 165-Ball PBGA (TOP VIEW)
1
2
3
4
5
6
7
8
9
A
NC
A
CE
BWc
BWb
CE2
CKE
ADV
A
B
NC
A
CE2
BWd
BWa
CLK
WE
OE
A
10
11
A
NC
A
NC
C DQPc NC
VDDQ
VSS
VSS
VSS
VSS
VSS
VDDQ
NC
DQPb
D DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
E DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
F DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
G DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
H
NC
VDD
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
J
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
K DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
L
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
M DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
N DQPd NC
VDDQ
VSS
NC
NC
NC
VSS
VDDQ
NC
DQPa
P
NC
NC
A
A
TDI
A1*
TDO
A
A
A
NC
R MODE NC
A
A
TMS
A0*
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
WE
CLK
CKE
CE
CE2
CE2
BWx (x=a-d)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
Synchronous Clock
Clock Enable
Synchronous Chip Select
Synchronous Chip Select
Synchronous Chip Select
Synchronous Byte Write Inputs
Symbol
OE
ZZ
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQx
DQPx
VDDQ
VSS
Pin Name
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev. B
08/26/05