IS62LV12816BLL Datasheet, PDF (5/10 Pages) Integrated Silicon Solution, Inc – 128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS62LV12816BLL
ISSI ^®
POWER SUPPLY CHARACTERISTICS⁽¹⁾ (Over Operating Range)
-55
-70
-100
Symbol Parameter
Test Conditions
ICC
Vcc Dynamic Operating VCC = Max.,
Com.
Min. Max. Min. Max. Min. Max. Unit
— 40
— 30
— 20 mA
1
Supply Current
IOUT = 0 mA, f = fMAX
Ind.
— 45
— 35
— 25
ISB1
TTL Standby Current VCC = Max.,
Com.
— 0.4 — 0.4 — 0.4 mA
(TTL Inputs)
VIN = VIH or VIL
CE ≥ VIH , f = 0
Ind.
— 1.0 — 1.0 — 1.0
2
OR
ULB Control
VCC = Max., VIN = VIH or VIL
CE = VIL, f = 0, UB = VIH, LB = VIH
3
ISB2
CMOS Standby
VCC = Max.,
Com.
—5
—5
—5
µA
Current (CMOS Inputs) CE ≥ VCC – 0.2V,
Ind.
—5
—5
—5
VIN ≥ VCC – 0.2V, or
4
VIN ≤ 0.2V, f = 0
OR
ULB Control
VCC = Max., CE = VIL
5
VIN ≤ 0.2V, f = 0; UB / LB = VCC – 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
6
READ CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
7
Symbol Parameter
-55
-70
-100
Min. Max.
Min. Max.
Min. Max.
Unit
tRC
Read Cycle Time
55 —
70 —
100 —
ns
8
tAA
Address Access Time
—
55
—
70
— 100
ns
tOHA
Output Hold Time
10 —
10 —
15 —
ns
tACE
CE Access Time
—
55
—
70
— 100
ns
9
tDOE
OE Access Time
—
30
—
35
—
50
ns
tHZOE⁽²⁾ OE to High-Z Output
—
20
—
25
—
30
ns
tLZOE⁽²⁾ OE to Low-Z Output
5
—
5
—
5
—
ns
tHZCE⁽²⁾ CE to High-Z Output
0
20
0
25
0
30
ns
10
tLZCE⁽²⁾ CE to Low-Z Output
10 —
10 —
10 —
ns
tBA
LB, UB Access Time
—
55
—
70
— 100
ns
11
tHZB
LB, UB to High-Z Output 0
25
0
25
0
35
ns
tLZB
LB, UB to Low-Z Output 0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels of
0.4 to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
5
Rev. B
03/07/01