IS62WV2568DALL Datasheet, PDF (4/14 Pages) Integrated Silicon Solution, Inc – TTL compatible interface levels

IS62/65WV2568DALL,IS62/65WV2568DBLL
CAPACITANCE⁽¹⁾
Symbol Parameter
Conditions
Max.
Cin
Input Capacitance
Vin = 0V
8
Cout
Input/Output Capacitance
Vout = 0V
10
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
Unit
pF
pF
AC TEST CONDITIONS
Parameter

Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
62WV2568DALL
(Unit)
0.4V to Vcc-0.2V
5 ns
Vref
See Figures 1 and 2
62WV2568DBLL
(Unit)
0.4V to Vcc-0.3V
5ns
Vref
See Figures 1 and 2

R1(Ω)
R2(Ω)
Vref
Vtm
1.8V ± 10%
3070
3150
0.9V
1.8V
2.5V - 3.6V
3070
3150
1.5V
2.8V
AC TEST LOADS
R1
VTM
OUTPUT
30 pF
R2
Including
jig and
scope
Figure 1
4
R1
VTM
OUTPUT
5 pF
R2
Including
jig and
scope
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com
Rev.  C
05/24/2013