IS61NLF25636A Datasheet, PDF (27/37 Pages) Integrated Silicon Solution, Inc – 256K x 36 and 512K x 18 9Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM

IS61NLF25636A/IS61NVF25636A
IS61NLF51218A/IS61NVF51218A
TAP Electrical Characteristics Over the Operating Range^(1,2)
Symbol
Parameter
Test Conditions
VOH1
Output HIGH Voltage
IOH = –2.0 mA
VOH2
Output HIGH Voltage
IOH = –100 µA
VOL1
Output LOW Voltage
IOL = 2.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Leakage Current
VSS ≤ V I ≤ VDDQ
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ≤ VDD +1.5V for t ≤ tTCYC/2,
Undershoot: VIL (AC) ≤ 0.5V for t ≤ tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
ISSI ^®
Min.
1.7
2.1
—
—
1.7
–0.3
–10
Max.
—
—
0.7
0.2
VDD +0.3
0.7
10
Units
V
V
V
V
V
V
µA
TAP AC ELECTRICAL CHARACTERISTICS^(1,2) (OVER OPERATING RANGE)
Symbol Parameter
Min.
Max.
tTCYC
TCK Clock cycle time
100
—
fTF
TCK Clock frequency
—
10
tTH
TCK Clock HIGH
40
—
tTL
TCK Clock LOW
40
—
tTMSS TMS setup to TCK Clock Rise
10
—
tTDIS
TDI setup to TCK Clock Rise
10
—
tCS
Capture setup to TCK Rise
10
—
tTMSH TMS hold after TCK Clock Rise
10
—
tTDIH
TDI Hold after Clock Rise
10
—
tCH
Capture hold after Clock Rise
10
—
tTDOV
TCK LOW to TDO valid
—
20
tTDOX TCK LOW to TDO invalid
0
—
Notes:
1. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Unit
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
27
Rev. B
08/26/05