IS49NLC96400A Datasheet, PDF (24/36 Pages) Integrated Silicon Solution, Inc – Reduced cycle time

IS49NLC96400A, IS49NLC18320A, IS49NLC36160A
0
1
2
3
4
5
6
7
8
9
CK#
CK
Command WR
NOP
RD
RD
NOP
NOP
NOP
NOP
NOP
NOP
Address BA1,A1
DKx
DKx#
DQ
BA2, A2
BA3, A3
Write Latency = 5
Read Latency = 4
D1-1 D1-2
Q2-1 Q2-2 Q3-1 Q3-2
QVLD
QKx
QKx#
Don’t Care
Undefined
Write Followed by Read: BL=2 RL=4 & WL=5
3.9 Auto Refresh Command (AREF)
The Auto Refresh command performs a refresh cycle on one row of a specific bank of the memory. Only bank addresses
are required together with the control the pins. Therefore, Auto Refresh commands can be issued on subsequent CK
clock cycles on both multiplexed and non-multiplexed address mode. Any command following an Auto Refresh command
must meet a tRC timing delay or later.
CK#
CK
QKx#
QKx
Command
Bank Address
0
1
t_CKH
t_CKL
t_CK
AREFx
BAx
AREFy
BAy
2
3
4
5
6
t_RC
NOP
NOP
NOP
t_RC
ANYCOMx
BAx
ANYCOMy
BAy
Don’t Care
AREF example in t_RC(t_CK)=5 option: Configuration=5
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00A, 9/10/2014
24