IS66WVE1M16EALL-70BLI Datasheet, PDF (23/34 Pages) Integrated Silicon Solution, Inc – 16Mb Async/Page PSRAM

IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
Table 13 . Asynchronous WRITE Cycle Timing Requirements
Sym
bol
Parameter
t_AS Address setup Time
t_AW Address valid to end of write
t_BW Byte select to end of write
t_CPH CE# HIGH time during write
t_CW Chip enable to end of Write
t_DH Data hold from write time
t_DW Data write setup time
t_LZ Chip enable to Low-Z output
t_OW End write to Low-Z output
t_WC Write cycle time
t_WHZ Write to High-Z output
t_WP Write pulse width
t_WPH Write pulse width HIGH
t_WR Write recovery time
-55
Min
Max
0
55
55
5
55
0
23
10
5
55
8
46
10
0
-70
Unit
Min
Max
0
ns
70
ns
70
ns
5
ns
70
ns
0
ns
23
ns
10
ns
5
ns
70
ns
8
ns
46
ns
10
ns
0
ns
Notes
1
1
2
4
3
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The
Low-Z timings measure a 100mV transition away from the High-Z (VDDQ/2) level toward
either VOH or VOL.
3. Write address is valid prior to or coincident with CE# LOW transition and is valid prior to or coincident with
CE# HIGH transition.
4. WE# LOW must be limited to t_CEM.
Rev. C | Oct. 2015
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