IS66WVE1M16EALL-70BLI Datasheet, PDF (22/34 Pages) Integrated Silicon Solution, Inc – 16Mb Async/Page PSRAM

IS66/67WVE1M16EALL/EBLL/ECLL
IS66/67WVE1M16TALL/TBLL/TCLL
AC Characteristics
Table 12 . Asynchronous READ Cycle Timing Requirements
Symbol
Parameter
-55
Min Max
-70
Min Max
Unit Notes
t_AA
Address Acess Time
60
70
ns
t_APA
Page access Time
25
25
ns
t_BA
LB# /UB# access Time
60
70
ns
t_BHZ
LB#/UB# disable to High-Z output
8
8
ns
1
t_BLZ
LB#/UB# enable to Low-Z output
10
10
ns
2
t_CEM
Maximum CE# pulse width
8
8
us
4
t_CO
Chip select access time
60
70
ns
t_HZ
Chip disable to High-Z output
8
8
ns
1
t_LZ
Chip enable to Low-Z output
10
10
ns
2
t_OE
Output enable to valid output
20
20
ns
t_OH
Output hold from address change
5
5
ns
t_OHZ Output disable to High-Z output
8
8
ns
1
t_OLZ
Output enable to Low-Z output
3
3
ns
2
t_PC
Page cycle time
20
20
ns
t_RC
Read cycle time
60
70
ns
3
t_CPH
CE# HIGH time Read
5
5
ns
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 9. The High-Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 9. The Low-Z timings
measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or VOL.
3. Address is valid prior to or coincident with CE# LOW transition and is valid prior to or coincident with CE#
HIGH transition.
4. t_CEM during Asynchronous Read Operation does not apply to IS66/67WVE1M16TALL/BLL/CLL
Rev. C | Oct. 2015
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