IS61QDB22M18A Datasheet, PDF (17/29 Pages) Integrated Silicon Solution, Inc – 1Mx36 and 2Mx18 configuration available

IS61QDB22M18B
IS61QDB21M36B
AC Timing Characteristics
(Over the Operating Temperature Range, V_DD=1.8V±5%, V_DDQ=1.5V/1.8V)
Parameter
Symbol
30 (333MHz)
Min Max
33 (300MHz)
Min Max
40 (250MHz)
Min Max
unit notes
Clock
Clock Cycle Time (K, K#,C,C#)
tKHKH
3.00 8.4 3.33 8.4 4.00 8.4
ns
Clock Phase Jitter (K, K#,C,C#)
tKC var
0.3
0.3
0.3
ns
4
Clock High Time (K, K#,C,C#)
tKHKL
0.4
0.4
0.4
cycle
Clock Low Time (K, K#,C,C#)
tKLKH
0.4
0.4
0.4
cycle
Clock to Clock (K_H→ K#_H, C_H→ C#_H)
tKHK#H
1.35
1.50
1.80
ns
Clock to Data Clock (K > C, K# > C#)
tKHCH
0
1.35
0 1.48
0
1.8
ns
DLL Lock Time (K,C)
tKC lock
1024
1024
1024
cycles
5
Doff Low period to DLL reset
tDoffLowToReset ₅
5
5
ns
K static to DLL reset
tKCreset
30
30
30
ns
Output Times
C,C# High to Output Valid
C,C# High to Output Hold
C,C# High to Echo Clock Valid
C,C# High to Echo Clock Hold
CQ, CQ# High to Output Valid
CQ, CQ# High to Output Hold
C,C# High to Output High-Z
C,C# High to Output Low-Z
Setup Times
tCHQV
0.45
0.45
0.45
ns
1,3
tCHQX
-
0.45
-
0.45
-0.45
ns
1,3
tCHCQV
0.45
0.45
0.45
ns
1
tCHCQX
-
0.45
-
0.45
-0.45
ns
1
tCQHQV
0.30
0.30
0.30
ns
1,3
tCQHQX
-
0.30
-
0.30
-0.30
ns
1,3
tCHQZ
0.45
0.45
0.45
ns
1,3
tCHQX1
-
0.45
-
0.45
-0.45
ns
1,3
Address valid to K rising edge
R#,W# control inputs valid to K rising
edge
BW_x# control inputs valid to K rising
edge
Data-in valid to K, K# rising edge
tAVKH
0.30
tIVKH
0.30
tIVKH2
0.30
tDVKH
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
ns
2
ns
2
ns
2
ns
2
Hold Times
K rising edge to address hold
tKHAX
0.30
0.30
0.30
ns
2
K rising edge to R#,W# control inputs
hold
K rising edge to BW_x# control inputs
hold
tKHIX
0.30
tKHIX2
0.30
0.30
0.30
0.30
0.30
ns
2
ns
2
K, K# rising edge to data-in hold
tKHDX
0.30
0.30
0.30
ns
2
Notes:
1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. During normal operation, VIH, VIL, TRISE, and TFALL of inputs must be within 20% of VIH, VIL, TRISE, and TFALL of clock.
3. If C, C are tied high, then K, K become the references for C, C timing parameters.
4. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
5. V_DD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once V_DD and input clock are stable.
6. The data sheet parameters reflect tester guard bands and test setup variations.
7. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0 C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70 C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
Integrated Silicon Solution, Inc.- www.issi.com
17
Rev. B
10/02/2014