IS61QDB22M18A Datasheet, PDF (10/29 Pages) Integrated Silicon Solution, Inc – 1Mx36 and 2Mx18 configuration available

IS61QDB22M18B
IS61QDB21M36B
Timing Reference Diagram for Truth Table
The Timing Reference Diagram for Truth Table is helpful in understanding the Clock and Write Truth Tables, as it
shows the cycle relationship between clocks, address, data in, data out, and control signals. Read command is issued
at the beginning of cycle “t”. Write command is issued at the beginning of cycle “t+1”.
Cycle
t
t+1
t+2
t+3
t+4
t+5
K Clock
K# Clock
R#
W#
BWx#
Address
Data-In
Data-Out
C Clock
C# Clock
CQ Clock
CQ# Clock
A
B
C
D
DB
DB+1
DD
DD+1
QA
QA+1
QC
QC+1
Clock Truth Table
(Use the following table with the
Mode
Clock
K
Stop Clock
Stop
Controls
R#
W#
X
X
.)
Data In
D_B
D_B+1
Previous State
Previous State
Data Out
Q_A
Q_A+1
Previous State
Previous State
No Operation (NOP)
L→H
H
H
X
X
High-Z
High-Z
Read A
L→H
L
X
X
X
D_OUT at C# (t+1.5) D_OUT at C (t+2.0)
Write B
L→H
X
L
D_IN at K (t)
D_IN at K# (t+0.5)
X
X
Notes:
1. Internal burst counter is always fixed as two-bit.
2. X = “don’t care”; H = logic “1”; L = logic “0”.
3. A read operation is started when control signal R# is active low
4. A write operation is started when control signal W# is active low.
5. For timing definitions, refer to the AC Timing Characteristics table. Signals must meet AC specifications at timings indicated in parenthesis with
respect to switching clocks K, K#, C and C#.
Integrated Silicon Solution, Inc.- www.issi.com
10
Rev. B
10/02/2014