IS61NLP12832A Datasheet, PDF (17/29 Pages) Integrated Silicon Solution, Inc – 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A
ISSI ^®
READ/WRITE CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
Symbol Parameter
-250
Min. Max.
fmax
Clock Frequency
— 250
tKC
Cycle Time
4.0
—
tKH
Clock High Time
1.7
—
tKL
Clock Low Time
1.7
—
tKQ
Clock Access Time
—
2.6
tKQX⁽²⁾
Clock High to Output Invalid
0.8
—
tKQLZ^(2,3)
Clock High to Output Low-Z
0.8
—
tKQHZ^(2,3)
Clock High to Output High-Z
—
2.6
tOEQ
Output Enable to Output Valid
—
2.8
tOELZ^(2,3)
Output Enable to Output Low-Z
0
—
tOEHZ^(2,3)
Output Disable to Output High-Z
—
2.6
tAS
Address Setup Time
1.2
—
tWS
Read/Write Setup Time
1.2
—
tCES
Chip Enable Setup Time
1.2
—
tSE
Clock Enable Setup Time
1.2
—
tADVS
Address Advance Setup Time
1.2
—
tDS
Data Setup Time
1.2
—
tAH
Address Hold Time
0.3
—
tHE
Clock Enable Hold Time
0.3
—
tWH
Write Hold Time
0.3
—
tCEH
Chip Enable Hold Time
0.3
—
tADVH
Address Advance Hold Time
0.3
—
tDH
Data Hold Time
0.3
—
tPDS
ZZ High to Power Down
—
2
tPUS
ZZ Low to Power Down
—
2
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
-200
Min. Max.
— 200
5—
2—
2—
— 3.1
1.5 —
1—
— 3.0
— 3.1
0—
— 3.0
1.4 —
1.4 —
1.4 —
1.4 —
1.4 —
1.4 —
0.4 —
0.4 —
0.4 —
0.4 —
0.4 —
0.4 —
—2
—2
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
17
Rev. 00C
09/12/05