IS61NLP12832A Datasheet, PDF (15/29 Pages) Integrated Silicon Solution, Inc – 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE (NO WAIT) STATE BUS SRAM

IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A
CAPACITANCE^(1,2)
Symbol Parameter
Conditions
Max.
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
COUT
Input/Output Capacitance
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
See Figures 1 and 2
ISSI ^®
3.3V I/O OUTPUT LOAD EQUIVALENT
OUTPUT
Zo= 50Ω
Figure 1
50Ω
1.5V
+3.3V
317 Ω
OUTPUT
351 Ω
5 pF
Including
jig and
scope
Figure 2
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
15
Rev. 00C
09/12/05