IS61WV102416ALL Datasheet, PDF (16/21 Pages) Integrated Silicon Solution, Inc – 1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY

IS61WV102416ALL
IS61WV102416BLL
IS64WV102416BLL
ISSI ^®
AC WAVEFORMS
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) ^(1,3)
ADDRESS
t WC
ADDRESS 1
t WC
ADDRESS 2
OE
CE _LOW
t SA
WE
UB, LB
DOUT
DIN
t PBW
t HZWE
DATA UNDEFINED
WORD 1
HIGH-Z
t SD
DATAIN
VALID
t HA
t SA
t PBW
WORD 2
t HA
t LZWE
t HD
t SD
DATAIN
VALID
t HD
UB_CEWR4.eps
Notes:
1. The internalWritetimeisdefinedbytheoverlapofCE=LOW,UBand/orLB=LOW,andWE=LOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,but
any can be deasserted to terminate the Write. The tSA, tHA, tSD, and tHD timing is referenced to the rising or falling edge of the signal that terminates the Write.
2. TestedwithOEHIGHforaminimumof4nsbefore WE=LOWtoplacetheI/OinaHIGH-Zstate.
3. WEmaybeheldLOWacrossmanyaddresscyclesandtheLB,UBpinscanbeusedtocontroltheWritefunction.
16
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. A
02/13/06