IS66WV51216DALL Datasheet, PDF(14/17 Page) Integrated Silicon Solution, Inc – 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM

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IS66WV51216DALL Datasheet, PDF (14/17 Pages) Integrated Silicon Solution, Inc – 8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM

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IS66WV51216DALL

IS66/67WV51216DBLL

avoidable timing and recommendations

Figure 3b

CS or

UB & LB

â¥ 15us

Address

Figure 4

Notes:

1. PSRAM uses DRAM cell which needs a REFRESH action periodically to retain the information. This REFRESH action is per-

formed internally as part of a READ cycle or when the device is not selected. A hidden REFRESH action has to be executed

by the device at least once every 15ms.

2. Figure 2a shows a timing example in which consecutive READ cycles occurs in intervals less than the tRC spec while the

device is selected for a period of 15ms. This timing should be avoided because output data from these READ cycles are not

guaranteed to be valid due to violation of the tRC spec. This timing also prohibits the device from performing a hidden RE-

FRESH action properly. Examples on how to avoid the timing in Figure 2a are shown in Figure 2b and 2c.

3. Figure 3a shows a timing example in which a single WRITE operation is maintained for a period greater than 15ms. Since a

REFRESH action cannot be performed during a WRITE operation, information stored in the device will not be retained if this

timing occurs. A WRITE operation is initiated when active LOW signals WE, CS, UB and LB are enabled (logic LOW) but any

one of these signals can be disabled (logic HIGH) to complete the WRITE operation. Figure 3b is a timing example of using

signal CS being disabled to complete the WRITE operation.

4. Since a REFRESH action cannot be performed during a WRITE operation, consecutive WRITE cycles occurring for a total

period greater than 15ms are not permitted. However, executing consecutive WRITE cycles greater than 15ms is acceptable if

either WE, CS, or both UB and LB, are disabled (logic HIGH) for a period of at least 5ns or higher and can be done once or

multiple times. An example using CS signal is shown in Figure 4

Integrated Silicon Solution, Inc. â www.issi.com

Rev.â A

06/28/2011

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