IS61WV51216EDALL Datasheet, PDF (11/19 Pages) Integrated Silicon Solution, Inc – TTL compatible inputs and outputs

IS61WV51216EDALL
IS61/64WV51216EDBLL
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol
twc
tsce
taw

tha
tsa
tpwb
tpwe1
tpwe2
tsd
thd
thzwe⁽²⁾
tlzwe⁽²⁾
-8
-10
Parameter Min. Max. Min. Max. Unit
Write Cycle Time
CE to Write End
8
—
6.5 —
10 —
ns
8
—
ns
Address Setup Time
to Write End
6.5 —
8
—
ns
Address Hold from Write End
0
—
0
—
ns
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
WE Pulse Width (OE = LOW)
0
—
6.5 —
6.5 —
8.0 —
0
—
ns
8
—
ns
8
—
ns
10 —
ns
Data Setup to Write End
5
—
6
—
ns
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
0
—
— 3.5
2
—
0
—
­ns
—
5
ns
2
—
ns
Notes:
1.  Test conditions and output loading conditions are specified in the AC Test Conditions and AC Test Loads (Figure 1).
2.  Tested with the load in Figure 2.Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3.  The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW.All signals must be in valid states to initi-
ate a Write, but any one can go inactive to terminate the Write.The Data Input Setup and Hold timing are referenced to the rising
or falling edge of the signal that terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. A
02/20/2013