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IRFS3307PBF Datasheet, PDF (7/11 Pages) International Rectifier – High Efficiency Synchronous Rectification in SMPS | |||
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IRFB/S/SL3307PbF
+
Â
-
Â
RG
D.U.T
+
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
Â
Circuit Layout Considerations
ï ï ï ï·ï Low Stray Inductance
ï ï·ï ï Ground Plane
-
ï ï·ï ï Low Leakage Inductance
Current Transformer
-Â +
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform Diode Recovery
dv/dt
ï·ï ï dv/dt controlled by RG
ï·ï ï Driver same type as D.U.T.
VDD
+
ï·ï ï ISD controlled by Duty Factor "D"
-
ï·ï ï D.U.T. - Device Under Test
Re-Applied
Voltage
Body Diode
IInndduuccttoorr CCuurrerennt t
Forward Drop
Ripple ï£ 5%
* VGS = 5V for Logic Level Devices
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
* VGS=10V
VDD
ISD
V(BR)DSS
15V
tp
VDS
L
DRIVER
RG
2V0GVS
tp
D.U.T
IAS
0.01ï
+
- VDD
A
Fig 21a. Unclamped Inductive Test Circuit
IAS
Fig 21b. Unclamped Inductive Waveforms
LD
VDS
+
VDD -
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
D.U.T
Fig 22a. Switching Time Test Circuit
VDS
90%
10%
VGS
td(on) tr
td(off) tf
Fig 22b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
1K
Vgs(th)
Fig 23a. Gate Charge Test Circuit
www.irf.com
Qgs1 Qgs2 Qgd
Qgodr
Fig 23b. Gate Charge Waveform
7
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