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IRFP4368PBF_15 Datasheet, PDF (2/8 Pages) International Rectifier – High Efficiency Synchronous Rectification in SMPS | |||
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IRFP4368PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
V(BR)DSS
âV(BR)DSS/âTJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
75 âââ âââ V VGS = 0V, ID = 250µA
âââ 0.077 âââ V/°C Reference to 25°C, ID = 5mAd
âââ 1.46 1.85 m⦠VGS = 10V, ID = 195A g
2.0 âââ 4.0 V VDS = VGS, ID = 250µA
âââ âââ 20 µA VDS = 75V, VGS = 0V
IGSS
Gate-to-Source Forward Leakage
âââ âââ 250
âââ âââ 100
VDS = 75V, VGS = 0V, TJ = 125°C
nA VGS = 20V
Gate-to-Source Reverse Leakage
âââ âââ -100
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
gfs
Qg
Qgs
Qgd
Qsync
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
650 âââ âââ S VDS = 50V, ID = 195A
âââ 380 570 nC ID = 195A
âââ 79 âââ
VDS = 38V
âââ 105 âââ
VGS = 10V g
âââ 275 âââ
ID = 195A, VDS =0V, VGS = 10V
RG(int)
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Internal Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
âââ 0.80 âââ
âââ 43 âââ
âââ 220 âââ
âââ 170 âââ
âââ 260 âââ
âââ 19230 âââ
âââ 1670 âââ
âââ 770 âââ
â¦
ns VDD = 49V
ID = 195A
RG = 2.7â¦
VGS = 10V g
pF VGS = 0V
VDS = 50V
Æ = 100kHz
Coss eff. (ER) Effective Output Capacitance (Energy Related)i âââ 1700 âââ
Coss eff. (TR) Effective Output Capacitance (Time Related)h âââ 1410 âââ
VGS = 0V, VDS = 0V to 60V i
VGS = 0V, VDS = 0V to 60V h
Diode Characteristics
Symbol
Parameter
IS
Continuous Source Current
(Body Diode)
ISM
Pulsed Source Current
(Body Diode) di
VSD
Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
Reverse Recovery Current
ton
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
âââ âââ 350c A MOSFET symbol
D
showing the
âââ âââ 1280
integral reverse
G
p-n junction diode.
S
âââ âââ 1.3 V TJ = 25°C, IS = 195A, VGS = 0V g
âââ 130 200 ns TJ = 25°C
VR = 64V,
âââ 140 210
TJ = 125°C
âââ 450 680 nC TJ = 25°C
IF = 195A
di/dt = 100A/µs g
âââ 530 800
TJ = 125°C
âââ 9.1 âââ A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Calculated continuous current based on maximum allowable junction  ISD ⤠195A, di/dt ⤠1740A/µs, VDD ⤠V(BR)DSS, TJ ⤠175°C.
temperature. Bond wire current limit is 195A. Note that current
Â
Pulse width ⤠400µs; duty cycle ⤠2%.
limitations arising from heating of the device leads may occur with  Coss eff. (TR) is a fixed capacitance that gives the same charging time
some lead mounting arrangements. Refer to App Notes (AN-1140).
as Coss while VDS is rising from 0 to 80% VDSS.
 Repetitive rating; pulse width limited by max. junction
temperature.
 Limited by TJmax, starting TJ = 25°C, L = 0.022mH
RG = 25â¦, IAS = 195A, VGS =10V. Part not recommended for use
above this value.
 Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
 When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
 Rθ is measured at TJ approximately 90°C.
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