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CHL8550 Datasheet, PDF (13/15 Pages) International Rectifier – High.Efficiency Variable Gate MOSFET Driver | |||
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HighâEfficiency Variable Gate MOSFET Driver CHL8550
APPLICATION INFORMATION
BOOT STRAP CIRCUIT
Once the highâside MOSFET selection is made, the
bootstrap circuit can be defined. The integrated boot
diode of the CHL8550 reduces the external component
count for use in cost and space sensitive designs. For ultra
highâefficiency designs, an external boot strap diode is
recommended.
The bootstrap capacitor CBoot stores the charge and
provides the voltage required to drive the external highâ
side MOSFET gate. The minimum capacitor value can be
defined by:
CBoot = QHS MOSFET_gate / âVBoot
where,
ï· QHS MOSFET_gate is the total gate charge of the
highâside external MOSFET(s)
ï· âVBoot is the droop allowed on the boot capacitor
voltage (at the highâside MOSFET gate)
A series resistor, 1Ω to 4Ω, may be added to customize the
rise time of the highâside output. Slowing down this output
allows setting the phase node rising slew rate and limits
the surge current into the boot capacitor on startâup.
SUPPLY DECOUPLING CAPACITOR
VCC decoupling to the IR3598 is provided by a 0.1µF
bypass capacitor CVcc located close to the supply input pin.
A series resistor Rvcc, typically 10Ω, is added in series with
the supply voltage to filter high frequency ringing and
noise. A 1.0µF or higher capacitor is recommended for the
VDRV decoupling capacitor, CDRV.
PCB LAYOUT CONSIDERATIONS
PCB layout and design is important to driver performance
in voltage regulator circuits due to the high current slew
rate (di/dt) during MOSFET switching.
ï· Locate all power components in each phase as
close to each other as practically possible in order
to minimize parasitics and losses, allowing for
reasonable airflow.
ï· Input supply decoupling and bootstrap capacitors
should be physically located close to their
respective IC pins.
ï· High current paths like the gate driver traces
should be as wide and short as practically possible.
ï· Trace inductances to the highâ and lowâside
MOSFETs should be minimized.
ï· The ground connection of the IC should be as close
as possible to the lowâside MOSFET source.
ï· Use of a copper plane under and around the IC
and thermal vias to connect to buried copper
layers improves the thermal performance.
MOSFET stages should be well bypassed with capacitors
placed between the drain of the HIGHâside MOSFET and
the source of the LOWâside MOSFET.
13 December 6, 2011 | FINAL | V1.05
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