CHL8550 Datasheet, PDF (11/15 Pages) International Rectifier – High.Efficiency Variable Gate MOSFET Driver

High‐Efficiency Variable Gate MOSFET Driver _CHL8550
THEORY OF OPERATION
POWER‐ON RESET (POR)
The CHL8550 incorporates a power‐on reset feature.
This ensures that both the high‐ and low‐side output
drivers are made active only after the device supply
voltage has exceeded a certain minimum operating
threshold. The V_cc and V_drv supply is monitored and both
the drivers are set to the low state, holding both external
MOSFETs off. Once V_cc and V_drv crosses the rising POR
threshold, the CHL8550 is reset and the outputs are held in
the low state until a transition from tri‐state to active
operation is detected at the PWM input. During normal
operation the drivers continue to remain active until the
V_cc and V_drv falls below the falling POR threshold.
INTEGRATED BOOTSTRAP DIODE
The CHL8550 features an integrated bootstrap diode
to reduce external component count. This enables the
CHL8550 to be used effectively in cost and space sensitive
designs.
The bootstrap circuit is used to establish the gate voltage
for the high‐side driver. It consists of a diode and capacitor
connected between the SWITCH and BOOT pins of the
device. Integrating the diode within the CHL8550,
results in the need for an external boot capacitor only.
The bootstrap capacitor is charged through the diode
and injects this charge into the high‐side MOSFET input
capacitance when PWM signal goes high.
IR ACTIVE TRI‐LEVEL (ATL) PWM INPUT SIGNAL
The CHL8550 gate drivers are driven by a patented tri‐level
PWM control signal provided by the IR digital PWM
controllers. During normal operation, the rising and falling
edges of the PWM signal transitions between 0V and 1.8V
to switch the LO_GATE and HI_GATE. To force both driver
outputs low simultaneously, the PWM signal crosses a
tri‐state voltage level higher than the tri‐state HI_GATE
threshold. This threshold based tri‐state results in a very
fast disable for both the drivers, with only a small tri‐state
propagation delay. MOSFET switching resumes when the
PWM signal falls below the tri‐state threshold into the
normal operating voltage range.
This fast tri‐state operation eliminates the need for any
tri‐state hold‐off time of the PWM signal to dwell in the
shutdown window. Dedicated disable or enable pins are
not required which simplifies the routing and layout in
applications with a limited number of board layers. It also
provides switching free of shoot through for slow PWM
transition times of up to 20ns. The CHL8550 is therefore
tolerant of stray capacitance on the PWM signal lines.
The CHL8550 provides a 1.0mA typical pull‐up current to
drive the PWM input to the tri‐state condition of 3.3V
when the PWM controller output is in its high impedance
state. The 1.0mA typical current is designed for driving
worst case stray capacitances and transition the CHL8550
into the tri‐state condition rapidly to avoid a prolonged
period of conduction of the high‐ or low‐side MOSFETs
during faults. Immediately after the driver is driven into
the tri‐state mode, the 1mA current is disables such that
power is conserved.
DIODE EMULATION DURING LOAD RELEASE
One advantage of this fast tri‐state scheme is the ability
to quickly turn‐off all low‐side MOSFETs during a load
release event. This is known as diode emulation since all
the load current is forced to flow momentarily through the
body diodes of the MOSFETs. This results in a much lower
overshoot on the output voltage as can be seen in Figure 7
below.
I_out 105A to 10A
V_out without diode emulation
Overshoots ~25mV over 0A level
V_out with Diode Emulation
Overshoot within 0A level
Results in reduction of 30mV
overshoot
Figure 7: Output Voltage Overshoot Reduction
with Diode Emulation
START UP
During initial startup, the CHL8550 holds both high‐ and
low‐side drivers low even after POR threshold is reached.
This mode is maintained while the PWM signal is pulled
to the tri‐state threshold level greater than the tri‐state
HI_GATE threshold and until it transitions out of tri‐state.
It is this initial transition out of the tri‐state which enables
both drivers to switch based on the normal PWM voltage
levels.
11 December 6, 2011 | FINAL | V1.05