X4163-65 Datasheet, PDF (9/22 Pages) Intersil Corporation – Selectable watchdog timer

X4163, X4165
Writing to the Control Register
Changing any of the nonvolatile bits of the control reg-
ister requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
– Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
– Write a value to the Control Register that has all the
control bits set to the desired state. This can be rep-
resented as 0xys t01r in binary, where xy are the
WD bits. (Operation preceeded by a start and ended
with a stop). Since this is a nonvolatile write cycle it
will take up to 10ms to complete. The RWEL bit is
reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2
is set to ‘1’ in this third step (0xys t11r) then the
RWEL bit is set, but the BP2, BP1, BP0, WD1 and
WD0 bits remain unchanged. Writing a second byte
to the control register is not allowed. Doing so aborts
the write operation and returns a NACK.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
Figure 5. Valid Data Changes on the SDA Bus
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
SCL
SDA
Data Stable
Data Change
Data Stable
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FN8120.2
November 26, 2007