X4163-65 Datasheet, PDF (14/22 Pages) Intersil Corporation – Selectable watchdog timer

X4163, X4165
Figure 14. Sequential Read Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
Slave
Address
A
A
A
C
C
C
K
K
K
t
o
p
1
A
C
Data
K
(1)
Data
(2)
Data
(n-1)
Data
(n)
(n is any integer greater than 1)
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to address 0000_H and the device continues
to output data for each acknowledge received. Refer
to Figure 14 for the acknowledge and data transfer
sequence.
X4163, X4165 Addressing
SLAVE ADDRESS BYTE
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
– a device type identifier that is ‘1010’ to access the
array.
– one bits of ‘0’.
– next two bits are the device address.
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is undefined on a power up condition.
14
FN8120.2
November 26, 2007