ISL78420ARTBZ-T Datasheet, PDF (9/16 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
Typical Performance Curves (Continued)
120
110
100
I_DD
90
80
70
60
50
40
I_HB
30
20
10
0
0
5
10
15
20
V_DD, V_HB (V)
FIGURE 15. QUIESCENT CURRENT vs VOLTAGE
1.00
0.10
0.01
1^.10^-3
1^.10^-4
1^.10^-5
1^.10^-6
0.3
0.4
0.5
0.6
0.7
0.8
FORWARD VOLTAGE (V)
FIGURE 16. BOOTSTRAP DIODE I-V CHARACTERISTICS
120
100
80
60
40
20
0
12
13
14
15
16
V_HS TO V_SS VOLTAGE (V)
FIGURE 17. V_HS VOLTAGE vs V_DD VOLTAGE
Functional Description
Functional Overview
When connected to a half bridge, the output of the bridge on the
HS node follows the PWM input. In other words, when the PWM
input is high, the high-side bridge FET is turned on and the
low-side FET is off. When the PWM input is low, the low-side
bridge FET is turned on and the high-side is turned off. The
enable pin (EN), when low, drives both outputs to a low state.
A unique feature of the ISL78420 is the tri-level logic of the PWM
input. The logic thresholds of the PWM input is divided into 3
levels. A logic low ensures that the output of the low-side bridge
FET is on and the high-side FET is off. A logic high ensures that
the high-side bridge FET is on and the low-side FET is off. When
the logic input is midrange (2.5V), both the high and low side
FETs are off. This driver is designed to work in conjunction with
the ISL78220, “6-Phase Interleaved Boost PWM Controller with
Light Load Efficiency Enhancement”.
When the PWM input transitions high or low, it is necessary to
ensure that both bridge FETS are not on at the same time to
prevent shoot-through currents (break before make). The internal
programmable timers delay the rising edge of either output
resulting with both outputs being off before either of the bridge
FETs are driven on. An 8kΩ resistor connected between R_DT and
VSS results in a nominal dead time of 220ns. An 80kΩ results
with a minimum nominal dead time of 25ns. Resistors values
less than 8k and greater than 80k are not recommended.
While the voltage of the input signal to the PWM is within the
boundaries of the mid-level logic, the outputs are in a dead time
state because both outputs are off. The actual delay time, as
programed by the R_DT value, begins when the high or low logic
levels are transitioned. The period while the input logic in the
mid-level range, is consequently added to the programmed dead
time period. This may be a consideration when selecting the R_DT
value.
The high-side driver bias is established by the boot capacitor
connected between HB and HS. The charge on the boot capacitor
is provided by the internal boot diode that is connected to VDD.
The current path to charge the boot capacitor occurs when the
low-side bridge FET is on. This charge current is limited in
amplitude by the inherent resistance of the boot diode and by the
drain-source voltage of the low-side FET. Assuming that the on
time of the low-side FET is sufficiently long to fully charge the
boot capacitor, the boot voltage will charge very close to VDD
(less the boot diode drop and the on-voltage of the low-side
bridge FET).
When the PWM input transitions high, the high-side bridge FET is
driven on after the dead time. Because the HS node is connected
9
FN8296.2
January 24, 2014