ISL78420ARTBZ-T Datasheet, PDF (5/16 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
Electrical Specifications V_DD = V_HB = 12V, V_SS = V_HS = 0V, R_DT = 0_K, PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
PARAMETERS
SYMBOL
TEST CONDITIONS
T_A = +25°C
MIN TYP MAX
T_A = -40°C to +125°C
MIN
(Note 9)
MAX
(Note 9)
UNITS
EN Input
Low Level Input Threshold
High Level Input Threshold
EN Pull-up Resistance
UNDERVOLTAGE PROTECTION
V_ENL
V_ENH
R_pu
1.4 1.8 -
1.2
- 1.8 2.2
-
- 210 -
100
-
V
2.4
V
320
kΩ
V_DD Rising Threshold
V_DD Threshold Hysteresis
HB Rising Threshold
HB Threshold Hysteresis
BOOTSTRAP DIODE
V_DDR
V_DDH
V_HBR
V_HBH
6.8 7.3 7.8
6.5
- 0.6 -
-
6.2 6.9 7.5
5.9
- 0.6 -
-
8.1
V
-
V
7.8
V
-
V
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
LO GATE DRIVER
V_DL
I_VDD-HB = 100mA
V_DH
I_VDD-HB = 100mA
R_D
I_VDD-HB = 100mA
- 0.6 0.7
-
- 0.7 0.9
-
- 0.8 1
-
0.8
V
1
V
1.5
Ω
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
Peak Pull-Down Current
HO GATE DRIVER
V_OLL
V_OHL
I_OHL
I_OLL
I_LO = 100mA
I_LO = -100mA, V_OHL = V_DD - V_LO
V_LO = 0V
V_LO = 12V
- 0.25 0.4
-
- 0.25 0.4
-
-
2
-
-
-
2
-
-
0.5
V
0.5
V
-
A
-
A
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
Peak Pull-Down Current
V_OLH
V_OHH
I_OHH
I_OLH
I_HO = 100mA
I_HO = -100mA, V_OHH = V_HB - V_HO
V_HO = 0V
V_HO = 12V
- 0.25 0.4
-
- 0.25 0.4
-
-
2
-
-
-
2
-
-
0.5
V
0.5
V
-
A
-
A
Switching Specifications V_DD = V_HB = 12V, V_SS = V_HS = 0V, R_DT = 0kΩ, No Load on LO or HO, Unless Otherwise Specified. Boldface
limits apply over the operating temperature range, -40°C to +125°C.
PARAMETERS
SYMBOL
TEST
CONDITIONS
T_J = +25°C
MIN TYPE MAX
T_J = -40°C to +125°C
MIN
(Note 9)
MAX
(Note 9)
UNITS
HO Turn-Off Propagation Delay
PWM Falling to HO Falling
t_PLHO
-
32 50
-
60
ns
LO Turn-Off Propagation Delay
PWM Rising to LO Falling
t_PLLO
-
32 50
-
60
ns
Minimum Dead-Time Delay (Note 10)
HO Falling to LO Rising
t_DTHLmin R_DT = 80k,
PWM 1 to 0
15 35 50
10
60
ns
Minimum Dead-Time Delay (Note 10)
LO Falling to HO Rising
t_DTLHmin R_DT = 80k
PWM 0 to 1
15 25 50
10
60
ns
Maximum Dead-Time Delay (Note 10)
HO Falling to LO Rising
t_DTHLmax R_DT = 8k,
PWM 1 to 0
150 220 300
-
-
ns
5
FN8296.2
January 24, 2014