ISL78420ARTBZ-T Datasheet, PDF (10/16 Pages) Intersil Corporation – 100V, 2A Peak, Half-Bridge Driver with Tri-Level PWM Input and Adjustable Dead-Time

ISL78420
to the source of the high-side FET, the HS node will rise almost to
the level of the bridge voltage (less the conduction voltage across
the bridge FET). Because the boot capacitor voltage is referenced
to the source voltage of the high-side FET, the HB node is V_DD
volts above the HS node and the boot diode is reversed biased.
Because the high-side driver circuit is referenced to the HS node,
the HO output is now approximately VHB + VBRIDGE above
ground.
During the low to high transition of the HS node, the boot
capacitor sources the necessary gate charge to fully enhance the
high-side bridge FET gate. After the gate is fully charged, the boot
capacitor no longer sources the charge to the gate but continues
to provide bias current to the high-side driver. It is clear that the
charge of the boot capacitor must be substantially larger than
the required charge of the high-side FET and high-side driver
otherwise the boot voltage will sag excessively. If the boot
capacitor value is too small for the required maximum of on-time
of the high-side FET, the high-side UV lockout may engage
resulting with an unexpected operation.
Application Information
Selecting the Boot Capacitor Value
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the driven FET without
causing the boot voltage to sag excessively. In practice, the boot
capacitor should have a total charge that is approximately 20x
the gate charge of the driven power FET for a 5% drop in voltage
after the charge has been transferred from the boot capacitor to
the gate capacitance.
The following parameters are required to calculate the value of
the boot capacitor for a specific amount of voltage droop. In this
example, the values used are arbitrary. They should be changed
to comply with the actual application.
V_DD = 10V
V_DD can be any value between 7 and 14VDC
V_HB = V_DD - 0.6V = V_HO High side driver bias voltage (V_DD - boot diode
voltage) referenced to V_HS
Period = 1ms
This is the longest expected switching period
I_HB = 100µA
Worst case high side driver current when
xHO = high (this value is specified for V_DD =
12V but the error is not significant)
R_GS = 100kΩ
Ripple= 5%
Gate-source resistor (usually not needed)
Desired ripple voltage on the boot cap (larger
ripple is not recommended)
I_{gate_leak} = 100nA
Qgate80V = 64nC
From the FET vendor’s datasheet
From Figure 18
12
I_D = 33A
10
V_DS = 80V
V_DS = 50V
8
V_DS = 20V
6
4
2
0
0 10 20 30 40 50 60 70 80
QG TOTAL GATE CHARGE (nC)
FIGURE 18. TYPICAL GATE CHARGE OF A POWER FET
The following equations calculate the total charge required for
the Period. These equations assume that all of the parameters
are constant during the period duration. The error is insignificant
if the ripple is small.
Q_C = Q_gate80V + Period × I_HB + V_HO ⁄ (R_GS + I_{gate_leak}) (EQ. 1)
C_boot = Q_C ⁄ (Ripple^∗VDD)
C_boot = 0.52μF
(EQ. 2)
If the gate to source resistor is removed (R_GS is usually not
needed or recommended), then:
C_boot = 0.33µF
10
FN8296.2
January 24, 2014