ISL72026SEH Datasheet, PDF (9/18 Pages) Intersil Corporation – 3.3V Radiation Tolerant CAN Transceiver, 1Mbps, Listen Mode, Loopback

ISL72026SEH
Test Circuits and Waveforms (Continued)
RS
CAN_H
V_IN
LBK
V_OD
60Ω
D
CAN_L
±1%
V_IN
R
GND
V_O
15pF ±20%
VO
50%
50%
V_CC
0V
V_OH
V_OL
t L - DOM
V_IN = 125kHz, 0V to V_CC, Duty Cycle 50%, t_r = t_f ≤ 6ns
FIGURE 16A. LISTEN TO VALID DOMINANT TIME TEST CIRCUIT
FIGURE 16B. LISTEN TO VALID DOMINANT TIME MEASUREMENT
POINTS
FIGURE 16. LISTEN TO VALID DOMINANT TIME
0Ω,10kΩ,50kΩ
RS
CAN H
LBK
D
CAN L
V_IN
R
GND
V_O
15pF ±20%
60Ω
±1%
50%
V_IN
t_(LOOP2)
50%
V_O
50%
t_(LOOP1)
50%
VCC
0V
V_OH
V_OL
V_IN = 125kHz, Duty Cycle 50%, t_r = t_f ≤ 6ns.
FIGURE 17A. TOTAL LOOP DELAY TEST CIRCUIT
FIGURE 17B. TOTAL LOOP DELAY MEASUREMENT POINTS
FIGURE 17. TOTAL LOOP DELAY
0Ω,10kΩ,50kΩ
VCC
V_IN
RS
LBK
D
R
V_O
15pF ±20%
CAN_H
CAN_L
60Ω
±1%
+
V_OD = 2.3V
-
GND
V_IN
V_O
V_OD
50%
t_(LBK1)
50%
50%
t_(LBK2)
50%
t_(LBK) = t_(LBK1) = t_(LBK2)
V_CC
0V
V_OH
V_OL
= +2.3V
V_IN = 125kHz, 0V to V_CC, Duty Cycle 50%, t_r = t_f ≤ 6ns
FIGURE 18A. LOOP BACK DELAY TO DOMINANT TIME TEST CIRCUIT
FIGURE 18B. LOOP BACK DELAY TO DOMINANT MEASUREMENT
POINTS
FIGURE 18. LOOP BACK DELAY
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9
FN8762.1
November 9, 2015