ISL6754_14 Datasheet, PDF (9/19 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

ISL6754
through a RC network to produce the desired sawtooth
waveform.
OUTUL and OUTUR - These outputs control the upper
bridge FETs and operate at a fixed 50% duty cycle in
alternate sequence. OUTUL controls the upper left FET and
OUTUR controls the upper right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the lower FET outputs, OUTLL and OUTLR.
RESDEL - Sets the resonant delay period between the
toggle of the upper FETs and the turn on of either of the
lower FETs. The voltage applied to RESDEL determines
when the upper FETs switch relative to a lower FET turning
on. Varying the control voltage from 0 to 2.00V increases the
resonant delay duration from 0 to 100% of the deadtime. The
control voltage divided by 2 represents the percent of the
deadtime equal to the resonant delay. In practice the
maximum resonant delay must be set lower than 2.00V to
ensure that the lower FETs, at maximum duty cycle, are OFF
prior to the switching of the upper FETs.
OUTLL and OUTLR - These outputs control the lower
bridge FETs, are pulse width modulated, and operate in
alternate sequence. OUTLL controls the lower left FET and
OUTLR controls the lower right FET. The left and right
designation may be switched as long as they are switched in
conjunction with the upper FET outputs, OUTUL and
OUTUR.
OUTLLN and OUTLRN - These outputs are the
complements of the PWM (lower) bridge FETs. OUTLLN is
the complement of OUTLL and OUTLRN is the complement
of OUTLR. These outputs are suitable for control of
synchronous rectifiers. The phase relationship between
each output and its complement is controlled by the voltage
applied to VADJ.
VADJ - A 0V to 5V control voltage applied to this input sets
the relative delay or advance between OUTLL/OUTLR and
OUTLLN/OUTLRN. The phase relationship between
OUTUL/OUTUR and OUTLL/OUTLR is maintained
regardless of the phase adjustment between OUTLL/OUTLR
and OUTLLN/OUTLRN.
Voltages below 2.425V result in OUTLLN/OUTLRN being
advanced relative to OUTLL/OUTLR. Voltages above
2.575V result in OUTLLN/OUTLRN being delayed relative to
OUTLL/OUTLR. A voltage of 2.50V ±75mV results in zero
phase difference. A weak internal 50% divider from VREF
results in no phase delay if this input is left floating.
The range of phase delay/advance is either zero or 40 to
300ns with the phase differential increasing as the voltage
deviation from 2.5V increases. The relationship between the
control voltage and phase differential is non-linear. The gain
(Δt/ΔV) is low for control voltages near 2.5V and rapidly
increases as the voltage approaches the extremes of the
control range. This behavior provides the user increased
accuracy when selecting a shorter delay/advance duration.
When the PWM outputs are delayed relative to the SR
outputs (VADJ < 2.425V), the delay time should not exceed
90% of the deadtime as determined by RTD and CT.
VERR - The control voltage input to the inverting input of the
PWM comparator. The output of an external error amplifier
(EA) is applied to this input, either directly or through an
opto-coupler, for closed loop regulation. VERR has a
nominal 1mA pull-up current source.
When VERR is driven by an opto-coupler or other current
source device, a pull-up resistor from VREF is required to
linearize the gain. Generally, a pull-up resistor on the order
of 5kΩ is acceptable.
FB - FB is the inverting inputs to the error amplifier (EA). The
amplifier may be used as the error amplifier for voltage
feedback or used as the average current limit amplifier (IEA).
If the amplifier is not used, FB should be grounded.
IOUT - Output of the 4X buffer amplifier of the sample and
hold circuitry that captures and averages the CS signal.
SS - Connect the soft-start timing capacitor between this pin
and GND to control the duration of soft-start. The value of
the capacitor and the internal current source determine the
rate of increase of the duty cycle during start-up.
SS may also be used to inhibit the outputs by grounding
through a small transistor in an open collector/drain
configuration.
CTBUF - CTBUF is the buffered output of the sawtooth
oscillator waveform present on CT and is capable of
sourcing 2mA. It is offset from ground by 0.40V and has a
nominal valley-to-peak gain of 2. It may be used for slope
compensation.
Functional Description
Features
The ISL6754 PWM is an excellent choice for low cost ZVS
full-bridge applications requiring adjustable synchronous
rectifier drive. With its many protection and control features,
a highly flexible design with minimal external components is
possible. Among its many features are a very accurate
overcurrent limit threshold, thermal protection, a buffered
sawtooth oscillator output suitable for slope compensation,
synchronous rectifier outputs with variable delay/advance
timing, and adjustable frequency.
If synchronous rectification is not required, please consider
the ISL6755 controller.
Oscillator
The ISL6754 has an oscillator with a programmable
frequency range to 2MHz, which can be programmed with a
resistor and capacitor.
9
FN6754.1
September 29, 2008