ISL6754_14 Datasheet, PDF (7/19 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

ISL6754
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application schematics” beginning on page 3. 9V < V_DD < 20V, RTD = 10.0kΩ, CT = 470pF,
T_A = -40°C to +105°C, Typical values are at T_A = +25°C; Parameters with MIN and/or MAX limits are 100%
tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START
Charging Current
SS = 3V
-60
-70
-80
μA
SS Clamp Voltage
4.410
4.500
4.590
V
SS Discharge Current
SS = 2V
10
-
-
mA
Reset Threshold Voltage
OUTPUT
T_A = +25°C
0.23
0.27
0.33
V
High Level Output Voltage (VOH)
I_OUT = -10mA, V_DD - VOH
Low Level Output Voltage (VOL)
I_OUT = 10mA, VOL - GND
Rise Time
C_OUT = 220pF, V_DD = 15V (Note 4)
Fall Time
C_OUT = 220pF, V_DD = 15V (Note 4)
UVLO Output Voltage Clamp
V_DD = 7V, I_LOAD = 1mA (Note 6)
Output Delay/Advance Range
V_ADJ = 2.50V
OUTLLN/OUTLRN relative to OUTLL/OUTLR
V_ADJ < 2.425V
V_ADJ > 2.575V
Delay/Advance Control Voltage Range
OUTLxN Delayed
OUTLLN/OUTLRN relative to OUTLL/OUTLR
OUTLxN Advanced
-
0.5
1.0
V
-
0.5
1.0
V
-
110
200
ns
-
90
150
ns
-
-
1.25
V
-
2
-
ns
-40
-
-300
ns
40
-
300
ns
2.575
-
5.000
V
0
-
2.425
V
V_ADJ Delay Time
THERMAL PROTECTION
T_A = +25°C (OUTLx Delayed) (Note 7)
V_ADJ = 0
V_ADJ = 0.5V
V_ADJ = 1.0V
V_ADJ = 1.5V
V_ADJ = 2.0V
T_A = +25°C (OUTLxN Delayed)
V_ADJ = V_REF
V_ADJ = V_REF - 0.5V
V_ADJ = V_REF - 1.0V
V_ADJ = V_REF - 1.5V
V_ADJ = V_REF - 2.0V
-
300
-
ns
-
105
-
ns
-
70
-
ns
-
55
-
ns
-
50
-
ns
-
300
-
ns
-
100
-
ns
-
68
-
ns
-
55
-
ns
-
48
-
ns
Thermal Shutdown
(Note 4)
-
140
-
°C
Thermal Shutdown Clear
(Note 4)
-
125
-
°C
Hysteresis, Internal Protection
(Note 4)
-
15
-
°C
NOTES:
4. Limits established by characterization and are not production tested.
5. This is the maximum duty cycle achievable using the specified values of RTD and CT. Larger or smaller maximum duty cycles may be obtained
using other values for these components. See Equations 1 through 3.
6. Adjust V_DD below the UVLO stop threshold prior to setting at 7V.
7. When OUTLx is delayed relative to OUTLxN (V_ADJ < 2.425V), the delay duration as set by V_ADJ should not exceed 90% of the CT discharge
time (deadtime) as determined by CT and RTD.
7
FN6754.1
September 29, 2008