ISL6754_14 Datasheet, PDF (15/19 Pages) Intersil Corporation – ZVS Full-Bridge PWM Controller with Adjustable Synchronous Rectifier Control

ISL6754
R9
R6
RCS
C4
1 _VREF
20
2
19
3 ^ISL6754 18
4
17
5 CT
16
6
15
7
14
8 RAMP
13
9 CS
12
10
GND 11
CT
FIGURE 11. ADDING SLOPE COMPENSATION USING CT
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 22
and 23 require modification. Equation 22 becomes:
V_e – ΔV_CS
=
-²----^D------^â‹---^R-----⁶---
R6 + R9
V
(EQ. 25)
and Equation 23 becomes:
R9
=
-⁽--²----^D------–----^V----^e-----+-----^Δ----^V----^C----^S----⁾----^â‹---^R----⁶--
V_e – ΔV_CS
Ω
(EQ. 26)
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain (>200) so as to
minimize the required base current. Whatever base current
is required reduces the charging current into CT and will
reduce the oscillator frequency.
ZVS Full-Bridge Operation
The ISL6754 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard-
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
CT
DEADTIME
OUTLL
OUTLR
PWM
PWM
PWM
PWM
OUTUR
RESONANT
DELAY
OUTUL
RESDEL
WINDOW
FIGURE 12. BRIDGE DRIVE SIGNAL TIMING
To understand how the ZVS method operates one must
include the parasitic elements of the circuit and examine a
full switching cycle.
VIN+
UL
UR
D1
L_L
VOUT+
RTN
LL
LR
D2
VIN-
FIGURE 13. IDEALIZED FULL-BRIDGE
In Figure 13, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
capacitance. Each switch is designated by its position, upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 14, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
are indicated by I_P and I_S, respectively.
VIN+
UL
I_P
LL
UR
L_L
LR
D1
I_S
D2
VOUT+
RTN
VIN-
FIGURE 14. UL - LR POWER TRANSFER CYCLE
15
FN6754.1
September 29, 2008