ISL6622 Datasheet, PDF (9/12 Pages) Intersil Corporation – VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

ISL6622
The total gate drive power losses are dissipated among the
resistive components along the transition path, as outlined in
Equation 4. The drive resistance dissipates a portion of the
total gate drive power losses, the rest will be dissipated by the
external gate resistors (R_G1 and R_G2) and the internal gate
resistors (R_GI1 and R_GI2) of MOSFETs. Figures 6 and 7 show
the typical upper and lower gate drives turn-on current paths.
P_DR = P_{DR_UP} + P_{DR_LOW} + I_Q • VCC
(EQ. 4)
P _{D R _UP}
=
⎛
⎜
⎝
-------------^R-----^H----^I--¹--------------
R_HI1 + R_EXT1
+
-_R----_L---_O-----₁^R----+-^L---^O-_R----¹-_E----_X----_T---₁- _{⎠⎟⎞}
•
P_{-----Q----g----_--Q-----1-}
2
P _{D R _LOW}
=
⎛
⎜
⎝
-------------^R-----^H----^I--²--------------
R_HI2 + R_EXT2
+
R^-----_L^---_O^-----₂^{R----+-L---O-}R^----2-_E^----_X^----_T^---₂^--_{⎠⎟⎞}
• ^P-----^Q----^g----^_--^Q-----²-
2
R_EXT1
=
R_G
1
+
R_{-----G-----I-1--}
N_Q1
R_EXT2
=
R_G
2
+
R_{-----G-----I-2--}
N_Q2
.
UVCC
BOOT
D
R_HI1
R_LO1
PHASE
C_GD
G
R_L1 ^RG1
C_GS
S
C_DS
Q1
FIGURE 6. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
LVCC
R_HI2
R_LO2
C_GD
G
R_L2 ^RG2
C_GS
S
D
C_DS
Q2
FIGURE 7. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
Application Information
Layout Considerations
During switching of the devices, the parasitic inductances of
the PCB and the power devices’ packaging (both upper and
lower MOSFETs) leads to ringing, possibly in excess of the
absolute maximum rating of the devices. Careful layout can
help minimize such unwanted stress. The following advice is
meant to lead to an optimized layout:
• Keep decoupling loops (LVCC-GND and BOOT-PHASE)
as short as possible.
• Minimize trace inductance, especially low-impedance
lines: all power traces (UGATE, PHASE, LGATE, GND,
LVCC) should be short and wide, as much as possible.
• Minimize the inductance of the PHASE node: ideally, the
source of the upper and the drain of the lower MOSFET
should be as close as thermally allowable.
• Minimize the input current loop: connect the source of the
lower MOSFET to ground as close to the transistor pin as
feasible; input capacitors (especially ceramic decoupling)
should be placed as close to the drain of upper and source
of lower MOSFETs as possible.
In addition, for improved heat dissipation, place copper
underneath the IC whether it has an exposed pad or not. The
copper area can be extended beyond the bottom area of the
IC and/or connected to buried power ground plane(s) with
thermal vias. This combination of vias for vertical heat
escape, extended surface copper islands, and buried planes
combine to allow the IC and the power switches to achieve
their full thermal potential.
Upper MOSFET Self Turn-On Effect at Start-up
Should the driver have insufficient bias voltage applied, its
outputs are floating. If the input bus is energized at a high
dV/dt rate while the driver outputs are floating, due to
self-coupling via the internal C_GD of the MOSFET, the gate
of the upper MOSFET could momentarily rise up to a level
greater than the threshold voltage of the device, potentially
turning on the upper switch. Therefore, if such a situation
could conceivably be encountered, it is a common practice
to place a resistor (R_UGPH) across the gate and source of
the upper MOSFET to suppress the Miller coupling effect.
The value of the resistor depends mainly on the input
voltage’s rate of rise, the C_GD/C_GS ratio, as well as the gate-
source threshold of the upper MOSFET. A higher dV/dt, a
lower C_DS/C_GS ratio, and a lower gate-source threshold
upper FET will require a smaller resistor to diminish the
effect of the internal capacitive coupling. For most
applications, the integrated 20kΩ resistor is sufficient, not
affecting normal performance and efficiency.
⎛
---------–----^V----^D-----^S-----------⎞
V _{G S _MILLER}
=
d_----V_---
dt
⋅
R
⋅
C_rs
s
⎜
⎜
⎜
1
–
e
d_----V_---
dt
⋅
R
⋅
Ci
s
⎟
s⎟
⎟
⎜
⎟
⎝
⎠
(EQ. 5)
R = R_UGPH + R_GI
C_rss = C_GD
C_iss = C_GD + C_GS
The coupling effect can be roughly estimated with
Equation 5, which assumes a fixed linear input ramp and
neglects the clamping effect of the body diode of the upper
drive and the bootstrap capacitor. Other parasitic
9
FN6470.2
October 30, 2008