ISL6622 Datasheet, PDF (8/12 Pages) Intersil Corporation – VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

ISL6622
Pre-POR Overvoltage Protection
While VCC is below its POR level, the upper gate is held low
and LGATE is connected to the PHASE pin via an internal
10kΩ (typically) resistor. By connecting the PHASE node to
the gate of the low side MOSFET, the driver offers some
passive protection to the load if the upper MOSFET(s) is or
becomes shorted. If the PHASE node goes higher than the
gate threshold of the lower MOSFET, it results in the
progressive turn-on of the device and the effective clamping
of the PHASE node’s rise. The actual PHASE node clamping
level depends on the lower MOSFET’s electrical
characteristics, as well as the characteristics of the input
supply and the path connecting it to the respective PHASE
node.
Internal Bootstrap Device
The ISL6622 features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor
from overcharging due to the large negative swing at the
trailing-edge of the PHASE node. This reduces the voltage
stress on the BOOT to PHASE pins.
The bootstrap capacitor must have a maximum voltage
rating well above the maximum voltage intended for UVCC.
Its minimum capacitance value can be estimated from
Equation 1:
C_{BOOT_CAP} ≥ _Δ-----_V---^Q-_B---^U-_O----^GO----^A-_T---^T_---_C-^E---_A----_P-
(EQ. 1)
Q_UGATE=
Q_{-----G-----1----}•_-----U_----V_-----C_-----C_--
V_GS1
•
N_Q1
where Q_G1 is the amount of gate charge per upper MOSFET
at V_GS1 gate-source voltage and N_Q1 is the number of
control MOSFETs. The ΔV_{BOOT_CAP} term is defined as the
allowable droop in the rail of the upper gate drive. Select
results are exemplified in Figure 5.
.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2 _20nC
Q_UGATE = 100nC
50nC
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV_{BOOT_CAP} (V)
FIGURE 5. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the
switching frequency (F_SW), the output drive impedance, the
layout resistance, and the selected MOSFET’s internal gate
resistance and total gate charge (Q_G). Calculating the power
dissipation in the driver for a desired application is critical to
ensure safe operation. Exceeding the maximum allowable
power dissipation level may push the IC beyond the maximum
recommended operating junction temperature. The DFN
package is more suitable for high frequency applications. See
“Layout Considerations” on page 9 for thermal impedance
improvement suggestions. The total gate drive power losses
due to the gate charge of MOSFETs and the driver’s internal
circuitry and their corresponding average driver current can
be estimated using Equations 2 and 3, respectively:
P_{Qg_TOT} = P_{Qg_Q1} + P_{Qg_Q2} + I_Q • VCC
P_{Q g _Q1}
=
Q_{-----G-----1----}•_-----U_----V_-----C_-----C_----²_--
V_GS1
•
F_S
W
•
N_Q
1
P _{Q g _Q2}
=
Q_{-----G-----2----}•_-----L_---V_-----C_-----C_----²_--
V_GS2
•
F_SW
•
N_Q2
(EQ. 2)
I_DR
=
⎛
⎜
⎝
Q_{-----G-----1----}•_-----U_----V_-----C_-----C_-----•_-----N_----Q-----1-
V_GS1
+
-^Q----^G-----²----^•-----^LV---^V--_G---^C-_S----^C₂-----^•-----^N----^Q-----²-_{⎠⎟⎞}
• F_SW + I_Q
(EQ. 3)
where the gate charge (Q_G1 and Q_G2) is defined at a
particular gate to source voltage (V_GS1 and V_GS2) in the
corresponding MOSFET datasheet; I_Q is the driver’s total
quiescent current with no load at both drive outputs; N_Q1
and N_Q2 are number of upper and lower MOSFETs,
respectively; UVCC and LVCC are the drive voltages for
both upper and lower FETs, respectively. The I_Q*VCC
product is the quiescent power of the driver without a load.
8
FN6470.2
October 30, 2008