ISL6622 Datasheet, PDF (6/12 Pages) Intersil Corporation – VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

PWM
UGATE
t_PDHU
t_RU
ISL6622
1.5V<PWM<3.2V
t_PDLU
t_FU
t_PDTS
1.0V<PWM<2.6V
t_{UG_OFF_DB}
t_PDTS
LGATE
t_PDLL
t_FL
t_PDHL
t_RL
t_TSSHD
FIGURE 1. TIMING DIAGRAM
Description
Operation and Adaptive Shoot-through Protection
Designed for high speed switching, the ISL6622 MOSFET
driver controls both high-side and low-side N-Channel FETs
from one externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Figure 1). After a short propagation delay
[t_PDLL], the lower gate begins to fall. Typical fall time [t_FL] is
provided in the “Electrical Specifications” on page 4. Following
a 25ns blanking period, adaptive shoot-through circuitry
monitors the LGATE voltage and turns on the upper gate
following a short delay time [t_PDHU] after the LGATE voltage
drops below ~1.75V. The upper gate drive then begins to rise
[t_RU] and the upper MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t_PDLU] is encountered before the upper
gate begins to fall [t_FU]. The adaptive shoot-through circuitry
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time [t_PDHL] after the upper
MOSFET’s PHASE voltage drops below +0.8V or 40ns after
the upper MOSFET’s gate voltage [UGATE-PHASE] drops
below ~1.75V. The lower gate then rises [t_RL], turning on the
lower MOSFET. These methods prevent both the lower and
upper MOSFETs from conducting simultaneously
(shoot-through), while adapting the dead time to the gate
charge characteristics of the MOSFETs being used.
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower MOSFET
conducts for a longer time during a switching period. The
lower gate driver is therefore sized much larger to meet this
application requirement. The 0.8Ω ON-resistance and 3A sink
current capability enable the lower gate driver to absorb the
current injected into the lower gate through the drain-to-gate
capacitor of the lower MOSFET and help prevent
shoot-through caused by the self turn-on of the lower
MOSFET due to high dV/dt of the switching node.
Advanced PWM Protocol (Patent Pending)
The advanced PWM protocol of ISL6622 is specifically
designed to work with Intersil VR11.1 controllers. When
ISL6622 detects a PSI protocol sent by an Intersil VR11.1
controller, it turns on diode emulation and GVOT (described
in next sections) operation; otherwise, it remains in normal
CCM PWM mode.
Another unique feature of ISL6622 and other Intersil drivers
is the addition of a three-state shutdown window to the PWM
input. If the PWM signal enters and remains within the
shutdown window for a set holdoff time, the driver outputs
are disabled and both MOSFET gates are pulled and held
low. The shutdown state is removed when the PWM signal
moves outside the shutdown window. Otherwise, the PWM
rising and falling thresholds outlined in the “Electrical
Specifications” on page 4 determine when the lower and
upper gates are enabled. This feature helps prevent a
negative transient on the output voltage when the output is
shut down, eliminating the Schottky diode that is used in
some systems for protecting the load from reversed output
voltage events.
Note that the LGATE will not turn off until the diode
emulation minimum ON-time of 350ns is expired for a PWM
low to tri-level (2.5V) transition.
Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6622 detects the zero current crossing of the output
inductor and turns off LGATE. This prevents the low side
MOSFET from sinking current and ensures that
discontinuous conduction mode (DCM) is achieved. The
LGATE has a minimum ON-time of 350ns in DCM mode.
6
FN6470.2
October 30, 2008