ISL6610 Datasheet, PDF (9/11 Pages) Intersil Corporation – Dual Synchronous Rectified MOSFET Drivers

ISL6610, ISL6610A
Therefore, if such a situation (when input bus powered up
before the bias of the controller and driver is ready) could
conceivably be encountered, it is a common practice to
place a resistor (R_UGPH) across the gate and source of the
upper MOSFET to suppress the Miller coupling effect. The
value of the resistor depends mainly on the input voltage’s
rate of rise, the C_GD/C_GS ratio, as well as the gate-source
threshold of the upper MOSFET. A higher dV/dt, a lower
C_DS/C_GS ratio, and a lower gate-source threshold upper
FET will require a smaller resistor to diminish the effect of
the internal capacitive coupling. For most applications, the
integrated 20kΩ typically sufficient, not affecting normal
performance and efficiency.
The coupling effect can be roughly estimated with the
following equations, which assume a fixed linear input ramp
and neglect the clamping effect of the body diode of the
upper drive and the bootstrap capacitor. Other parasitic
components such as lead inductances and PCB
capacitances are also not taken into account. These
equations are provided for guidance purpose only.
Therefore, the actual coupling effect should be examined
using a very high impedance (10MΩ or greater) probe to
ensure a safe design margin.
⎛
---------–----^V----^D-----^S-----------⎞
V _{G S _MILLER}
=
d_----V_---
dt
⋅
R
⋅
⎜
C_{r s s ⎜⎜} 1
–
d_----V_---
e ^dt
⋅
R
⋅
Cis
⎟
s⎟
⎟
⎜
⎟
⎝
⎠
(EQ. 5)
R = R_UGPH + R_GI
C_rss = C_GD
C_iss = C_GD + C_GS
VCC
DU
DL
BOOT
C_BOOT
C_GD
VIN
D
UGATE G
R_GI
C_DS
PHASE
C_GS
S
Q_UPPER
FIGURE 6. GATE TO SOURCE RESISTOR TO REDUCE
UPPER MOSFET MILLER COUPLING
9
FN6395.0
November 22, 2006